M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 656

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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16.3.6 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)
from on-chip peripheral I/O.
bit units; bits 5 to 0 (IFCn5 to IFCn0) can only be read or written in 8-bit units.
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The DTFR0 to DTFR3 registers are 8-bit registers that control the DMA transfer start trigger via interrupt requests
The interrupt requests set by these registers serve as DMA transfer start factors.
These registers can be read or written in 8-bit or 1-bit units. However, only bit 7 (DFn) can be read or written in 1-
Reset sets these registers to 00H.
Cautions 1. Be sure to follow the steps below when changing the DTFRn register settings.
2. An interrupt request from an on-chip peripheral I/O input in the standby mode (IDLE or STOP
3. If the start factor of DMA transfer is changed using the IFCn5 to IFCn0 bits, be sure to clear
• When the values to be set to the IFCn5 to IFCn0 bits are not set to the IFCm5 to IFCm0 bits
• When the values to be set to the IFCn5 to IFCn0 bits are set to the IFCm5 to IFCm0 bits of
mode) is held pending as a DMA transfer start factor. The held DMA start factor is executed
after restoring to the normal operation mode.
(0) the DFn bit by instruction immediately after.
of another channel (n = 0 to 3, m = 0 to 3, n ≠ m)
<1> Follow steps <3> to <5> when the DCHCn.Enn bit is cleared to 0, and follow steps <2>
<2> Stop the DMAn operation of the channel to be rewritten (DCHCn.INITn bit = 1).
<3> Change the DTFRn register settings. (Be sure to set the DFn bit to 0 and change the
<4> To clear a DMA transfer request, clear the DMA transfer request flag (DTFRn.DFn bit)
<5> Enable the DMAn operation (Enn bit = 1).
another channel (n = 0 to 3, m = 0 to 3, n ≠ m)
<1> Follow steps <4> to <6> when the DCHCn.Enn bit is cleared to 0, and follow steps <2>
<2> Stop the DMAn operation of the channel to be rewritten (DCHCn.INITn bit = 1).
<3> Stop the DMAm operation of the channel where the same values are set to the IFCm5
<4> Change the DTFRn register settings. (Be sure to set the DFn bit to 0 and change the
<5> To clear a DMA transfer request, clear the DMA transfer request flag (DTFRn.DFn bit)
<6> Enable the DMAn operation (Enn and Emm bits = 1).
to <5> when the Enn bit is set to 1.
settings in the 8-bit manipulation.)
to 0.
to <6> when the Enn bit is set to 1.
to IFCm0 bits as the values to be used to rewrite the IFCn5 to IFCn0 bits
(DCHCm.INITm bit = 0).
settings in the 8-bit manipulation.)
to 0.
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER)
User’s Manual U16543EJ4V0UD