M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 361

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
(c) Generation timing of compare match interrupt request signal (INTTQ0CCb)
CCRb buffer register
INTTQ0CCb signal
The timing of generation of the INTTQ0CCb signal in the PWM output mode differs from the timing of
INTTQ0CCb signals in other modes; the INTTQ0CCb signal is generated when the count value of the 16-
bit counter matches the value of the TQ0CCRb register.
Note Actually, the timing is delayed by one operating clock (f
Remark
Usually, the INTTQ0CCb signal is generated in synchronization with the next counting up after the count
value of the 16-bit counter matches the value of the TQ0CCRb register.
In the PWM output mode, however, it is generated one clock earlier. This is because the timing is changed
to match the change timing of the output signal of the TOQ0b pin.
TOQ0b pin output
16-bit counter
Count clock
b = 1 to 3
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
D
b
− 2
User’s Manual U16543EJ4V0UD
D
b
− 1
Note
Note
D
D
b
b
XX
).
D
b
+ 1
D
b
+ 2
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