M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 827

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

D.1 Major Revisions in This Edition
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Page
Addition of PG-FP5
Addition of description to 2.1 (1) Port pins
Modification of description in Table 3-2 System Register Numbers
Modification of description in 3.2.2 (6) Exception/debug trap status saving registers (DBPC, DBPSW)
Modification of description in 3.4.7 On-chip peripheral I/O registers
Addition of description to 4.3.4 (1) (e) Pull-up resistor option register 3 (PU3)
Modification of description in Table 4-16 Noise Eliminator
Addition of Figure 4-26 Example of Noise Elimination Timing
Modification of description in Figure 5-1 Clock Generator
Modification of description in 5.2 (5) Prescaler 1
Modification of description in Table 5-3 Operation Status of Each Clock
Addition of description to Table 6-1 TMPn Overview
Modification of description in 6.4 (2) TMPn control register 1 (TPnCTL1)
Modification of description in 6.4 (3) TMPm I/O control register 0 (TPmIOC0)
Modification of description in 6.6 (1) (a) Counter start operation
Addition of description to Figure 6-11 Register Setting for Interval Timer Mode Operation
Addition of description to Figure 6-12 Software Processing Flow in Interval Timer Mode
Addition of 6.6.1 (3) Operation by external event count input (TIPk0)
Addition of description to 6.6.2 External event count mode (TPkMD2 to TPkMD0 bits = 001)
Addition of description to Figure 6-18 Register Setting for Operation in External Event Count Mode
Addition of description to 6.6.2 (2) Operation timing in external event count mode
Modification of description in Figure 6-23 Configuration in External Trigger Pulse Output Mode
Modification of Figure 6-24 Basic Timing in External Trigger Pulse Output Mode
Addition of description to 6.6.3 External trigger pulse output mode (TPmMD2 to TPmMD0 bits = 010)
Modification of description in Figure 6-25 Setting of Registers in External Trigger Pulse Output Mode
Modification of figure in 6.6.3 (2) (b) 0%/100% output of PWM waveform
Modification of description in Figure 6-27 Configuration in One-Shot Pulse Output Mode
Modification of description in Figure 6-29 Setting of Registers in One-Shot Pulse Output Mode
Modification of description in Figure 6-30 Software Processing Flow in One-Shot Pulse Output Mode
Modification of figure in 6.6.4 (2) (a) Note on rewriting TPmCCRa register
Addition of description to Figure 6-33 Register Setting in PWM Output Mode
Modification of description in 6.6.5 (2) (a) Changing pulse width during operation
Modification of description in 6.6.5 (2) (b) 0%/100% output of PWM waveform
Modification of description in Figure 6-41 Configuration in Pulse Width Measurement Mode
Modification of description in 6.6.7 Pulse width measurement mode (TPkMD2 to TPkMD0 bits = 110)
Modification of description in Figure 6-43 Register Setting in Pulse Width Measurement Mode
Deletion of description in Figure 6-44 Software Processing Flow in Pulse Width Measurement Mode
APPENDIX D REVISION HISTORY
User’s Manual U16543EJ4V0UD
Description
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