M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 289

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 7-4. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Interval timer
External event counter
External trigger pulse output
One-shot pulse output
PWM output
Free-running timer
Pulse width measurement
(a) Function as compare register
(b) Function as capture register (TQ0CCR0 register only)
The following table shows the functions of the capture/compare register in each mode, and how to write data to
the compare register.
Notes 1. TMQ0 only
Remark
The TQnCCR0 register can be rewritten even when the TQnCTL0.TQnCE bit = 1.
The set value of the TQnCCR0 register is transferred to the CCR0 buffer register. When the value of the
16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal
(INTTQnCC0) is generated. If TOQn0 pin output is enabled at this time, the output of the TOQn0 pin is
inverted.
When the TQnCCR0 register is used as a cycle register in the interval timer mode, external event count
mode
the value of the 16-bit counter is cleared (0000H) if its count value matches the value of the CCR0 buffer
register.
The compare register is not cleared by the TQnCTL0.TQnCE bit = 0.
Note These modes can be set only in TMQ0. They cannot be set in TMQ1.
When the TQ0CCR0 register is used as a capture register in the free-running timer mode, the count value
of the 16-bit counter is stored in the TQ0CCR0 register if the valid edge of the capture trigger input pin
(TIQ00 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is
stored in the TQ0CCR0 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture
trigger input pin (TIQ00 pin) is detected.
Even if the capture operation and reading the TQ0CCR0 register conflict, the correct value of the
TQ0CCR0 register can be read.
The capture register is cleared by the TQ0CTL0.TQ0CE bit = 0.
2. Writing to the TQ0CCR1 register is the trigger.
Operation Mode
Note 1
Note
For anytime write and batch write, see 7.6 (2) Anytime write and batch write.
, external trigger pulse output mode
Note 1
Note 1
Note 1
Note 1
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
Compare register
Compare register
Compare register
Compare register
Compare register
Capture/compare register
Capture register
User’s Manual U16543EJ4V0UD
Capture/Compare Register
Note
, one-shot pulse output mode
Anytime write
Anytime write
Batch write
Anytime write
Batch write
Anytime write
None
How to Write Compare Register
Note 2
Note 2
Note
, or PWM output mode
287
Note
,