M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 363

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
• Compare operation
When the TQnCE bit is set to 1, 16-bit timer/event counter Q starts counting, and the output signals of the
TOQ00 to TOQ03 and TOQ10
set value of the TQnCCRa register, a compare match interrupt request signal (INTTQnCCa) is generated, and
the output signals of the TOQ00 to TOQ03 and TOQ10
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTQnOV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TQnOPT0.TQnOVF bit) is also set to 1. Confirm that the overflow flag is
set to 1 and then clear it to 0 by executing the CLR instruction via software.
The TQnCCRa register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected
at that time by anytime write, and compared with the count value.
Note V850E/IA4 only
Note The TOQ10 pin is provided only in the V850E/IA4.
Remark
TOQn0 pin
INTTQnCC0 signal
INTTQnCC1 signal
INTTQnCC2 signal
INTTQnCC3 signal
TQnCCR0 register
TQnCCR1 register
TQnCCR2 register
TQnCCR3 register
TOQ01 pin output
TOQ02 pin output
TOQ03 pin output
INTTQnOV signal
16-bit counter
Figure 7-34. Basic Timing in Free-Running Timer Mode (Compare Function)
TQnOVF bit
TQnCE bit
Note
n = 0, 1
a = 0 to 3
FFFFH
0000H
output
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
Note
pins are inverted. When the count value of the 16-bit counter later matches the
D
D
10
10
D
20
D
User’s Manual U16543EJ4V0UD
30
D
00
D
20
CLR instruction
Cleared to 0 by
D
30
D
D
00
11
D
Note
20
D
pins are inverted.
30
D
00
CLR instruction
Cleared to 0 by
D
11
D
11
D
21
D
31
D
D
01
21
D
31
CLR instruction
Cleared to 0 by
D
01
D
11
D
21
D
31
D
01
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