M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 652

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
16.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3)
to 3). These registers cannot be accessed during a DMA operation.
650
The DADC0 to DADC3 registers are 16-bit registers that control the DMA transfer mode for DMA channel n (n = 0
These registers can be read or written in 16-bit units.
Reset sets these registers to 0000H.
Cautions 1. The DSn0 bit sets how many bits of data is to be transferred.
2. Set the DADCn register when the target channel is in one of the following periods (the
If the transfer data size is set to 16 bits, transfer is always started from an address with the
lowest bit of the address aligned to “0”. In this case, transfer cannot be started from an odd
address.
operation is not guaranteed if the register is set at any other time).
• Period from system reset to the generation of the first DMA transfer request
• Period from completion of DMA transfer (after terminal count) to the generation of the next
• Period from forced termination of DMA transfer (after the DCHCn.INITn bit was set to 1) to
DMA transfer request
the generation of the next DMA transfer request
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER)
User’s Manual U16543EJ4V0UD

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