M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 723

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The timing and pin status at power-on are shown below.
(2) Reset operation (WDTRES) by overflow of watchdog timer (WDT)
Note
Remark
If the reset mode is set to reset upon overflow of the watchdog timer (WDT) (WDTM.WDM1 and WDTM.WDM0
bits = 10 or 11), the system is reset and each hardware is initialized to a specific state when WDT overflows
(INTWDT).
If the INTWDT interrupt request signal is generated, the RESF.RESFH4 bit is set to 1, indicating that internal
reset has occurred.
The operations during the reset period and after release of reset, other than the operation of the RESF
register, are the same as the reset operation by RESET pin input (see (1) Reset operation by RESET pin
input).
μ
PD70F3186 (V850E/IA4) only
The broken lines indicate the high-impedance state.
DDO
RESET (input)
Note
(output)
Figure 19-2. Timing and Pin Status at Power-On
EV
Pxx
V
DD
DD
CHAPTER 19 RESET FUNCTIONS
Undefined
Undefined
Undefined
User’s Manual U16543EJ4V0UD
5 V
During reset
2.5 V
Normal output
Reset release
Normal output
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