M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 592

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.7 Dedicated Baud Rate Generator
and generates a serial clock during transmission and reception with UARTAn. Regarding the serial clock, a dedicated
baud rate generator output can be selected for each channel.
590
The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter,
There is an 8-bit counter for transmission and another one for reception.
(1) Baud rate generator configuration
(a) Base clock
(b) Serial clock generation
Caution If the CPU clock (f
Remarks 1. n = 0, 1
When the UAnCTL0.UAnPWR bit is 1, the clock selected by the UAnCTL1.UAnCKS3 to
UAnCTL1.UAnCKS0 bits is supplied to the 8-bit counter. This clock is called the base clock (f
the UAnPWR bit = 0, f
A serial clock can be generated by setting the UAnCTL1 register and the UAnCTL2 register.
The base clock (f
The frequency division value for the 8-bit counter can be set using the UAnCTL2.UAnBRS7 to
UAnCTL2.UAnBRS0 bits.
f
f
f
XX
XX
XX
f
f
f
XX
XX
XX
f
f
f
/1024
/2048
/4096
XX
XX
XX
2. f
f
f
f
/128
/256
/512
XX
XX
XX
/16
/32
/64
/2
/4
/8
XX
UAnCKS3 to UAnCKS0
: Peripheral clock frequency
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
UCLK
UAnPWR bit
UAnCTL1:
Figure 14-10. Configuration of Baud Rate Generator
Selector
) is selected by the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits.
UCLK
CPU
is fixed to the low level.
) is slower than f
f
UCLK
User’s Manual U16543EJ4V0UD
UAnPWR, UAnTXE bit
UAnBRS7 to UAnBRS0
Match detector
8-bit counter
UCLK
UAnCTL2:
, UARTAn cannot be used.
(or UAnRXE bit)
1/2
Baud rate
UCLK
). When