M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 474

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
472
INTTQnCC0
CCR0 buffer
CCR1 buffer
INTTQnOV
The transfer timing is generated when the crest interrupt occurs, the period of counting up and counting down
changes, and an asymmetrical triangular wave is output.
Remarks 1. This is an example of the operation when the TQnOPT1.TQnICE bit = 1, TQnOPT1.TQnIOE bit =
TQnCCR0
TQnCCR1
pin output
TOQnT1
Transfer
register
register
counter
register
register
signal
timing
signal
16-bit
(b) Rewriting TQnCCR0 register
When rewriting the TQnCCR0 register in the intermittent batch mode, the output waveform differs
depending on where the occurrence of the crest or valley interrupt is specified by the interrupt culling
setting. The following figure illustrates the change of the output waveform when interrupts are culled.
L
2.
3. V850E/IA3: n = 0
0000H
0000H
0, TQnOPT1.TQnID4 to TQnOPT1.TQnID0 bits = 00001.
V850E/IA4: n = 0, 1
: Culled interrupt
Figure 10-32. Rewriting TQnCCR0 Register (When Crest Interrupt Is Set)
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CHAPTER 10 MOTOR CONTROL FUNCTION
User’s Manual U16543EJ4V0UD
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