M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 702

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.6.2 Debug trap
instruction.
700
The debug trap is an exception that can be acknowledged anytime and is generated by execution of the DBTRAP
When the debug trap is generated, the CPU performs the following processing.
(1) Operation
<1> Saves the restored PC to DBPC.
<2> Saves the current PSW to DBPSW.
<3> Sets the PSW.NP, PSW.EP and PSW.ID bits (1).
<4> Sets the handler address (00000060H) corresponding to the debug trap to the PC and transfers control.
The processing of the debug trap is shown below.
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
CPU processing
Figure 17-12. Debug Trap Processing
User’s Manual U16543EJ4V0UD
Debug monitor routine processing
DBPC
DBPSW
PSW.NP
PSW.EP
PSW.ID
PC
DBTRAP instruction
Restored PC
PSW
1
1
1
00000060H