M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 184

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
<R>
182
(3) TMPm I/O control register 0 (TPmIOC0)
Note The settings that can be realized differ from one channel to another. For details, see Tables 6-8 to 6-11.
Cautions 1. The TPmEST bit is valid only in the external trigger pulse output mode or one-shot pulse
The TPmIOC0 register is an 8-bit register that controls the timer output (TOP00, TOPm1 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Remark
2. External event count input is selected in the external event count mode regardless of the
3. Set the TPaSYE, TPkEEE, and TPnMD2 to TPnMD0 bits when the TPnCTL0.TPnCE bit = 0.
4. Be sure to clear bits 3 and 4 to “0”.
output mode. In any other mode, writing 1 to this bit is ignored.
value of the TPkEEE bit.
(The same value can be written when the TPnCE bit = 1.) The operation is not guaranteed
when rewriting is performed with the TPnCE bit = 1. If rewriting was mistakenly performed,
clear the TPnCE bit to 0 and then set the bits again.
TMP1 and TMP3 do not have the TP1IOC0 and TP3IOC0 registers in the V850E/IA3.
TMP1 does not have the TP1IOC0 register in the V850E/IA4.
TPnMD2
0
0
0
0
1
1
1
1
TPnMD1
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
0
0
1
1
0
0
1
1
TPnMD0
0
1
0
1
0
1
0
1
User’s Manual U16543EJ4V0UD
Interval timer mode
External event count mode
External trigger pulse output mode
One-shot pulse output mode
PWM output mode
Free-running timer mode
Pulse width measurement mode
Setting prohibited
Timer mode selection
Note
(2/2)

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