M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 50

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
3.2 CPU Register Set
register set and a dedicated system register set. All the registers have a 32-bit width.
48
The registers of the V850E/IA3 and V850E/IA4 can be classified into two categories: a general-purpose program
For details, refer to V850E1 Architecture User’s Manual.
(1) Program register set
31
31
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30 (Element pointer (EP))
r31 (Link pointer (LP))
PC (Program counter)
(Zero register)
(Assembler-reserved register)
(Stack pointer (SP))
(Global pointer (GP))
(Text pointer (TP))
Figure 3-1. CPU Register Set
CHAPTER 3 CPU FUNCTION
User’s Manual U16543EJ4V0UD
0
0
(2) System register set
31
EIPC (Status saving register during interrupt)
EIPSW (Status saving register during interrupt)
FEPC (Status saving register during NMI)
FEPSW (Status saving register during NMI)
ECR (Interrupt source register)
PSW (Program status word)
CTPC (Status saving register during CALLT execution)
CTPSW (Status saving register during CALLT execution)
DBPC (Status saving register during exception/debug trap)
DBPSW (Status saving register during exception/debug trap)
CTBP (CALLT base pointer)
0

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