M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 405

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.5 Operation
8.5.1 Operation in general-purpose timer mode
CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/GENERAL-PURPOSE TIMER (TIMER ENC1n)
TMENC1n can perform the following operations in the general-purpose timer mode.
(1) Interval operation (when TMC1n. ENMDn bit = 1)
(2) Free-running operation (when TMC1n.ENMDn bit = 0)
(3) Compare function
(4) Capture function
TMENC1n and the CM1n0 register always compare their values and the INTCMn0 interrupt request signal is
generated upon occurrence of a match. TMENC1n is cleared (0000H) at the count clock following the match.
Furthermore, when one more count clock is input, TMENC1n counts up to 0001H.
The interval time can be calculated by the following formula.
TMENC1n performs a full count operation from 0000H to FFFFH, and after the STATUS1n.TM1OVFn bit is set
(1), TMENC1n is cleared to 0000H at the next count clock and resumes counting.
The free-running cycle can be calculated by the following formula.
TMENC1n connects two compare register (CM1n0, CM1n1) channels and two capture/compare register
(CC1n0, CC1n1) channels.
When the TMENC1n count value and the set value of one of the compare registers match, a match interrupt
request signal (INTCMn0, INTCMn1, INTCCn0
operation, TMENC1n is cleared upon generation of the INTCMn0 interrupt.
Note This match interrupt request signal is generated when the CC1n0 and CC1n1 registers are set to the
TMENC1n connects two capture/compare register (CC1n0, CC1n1) channels.
When the CC1n0 and CC1n1 registers are set to the capture register mode, the value of TMENC1n is
captured in synchronization with the corresponding capture trigger signal.
Furthermore, an interrupt request signal (INTCCn0, INTCCn1) is generated by the valid edge of the TCUD1n
and TCLR1n input signals specified as the capture trigger signals.
The valid edge of the capture trigger is specified by the SESA1n register. If both the rising and falling edges
are selected as the capture trigger, it is possible to measure the width of a pulse input externally. If a single
edge is selected as the capture trigger, the input pulse cycle can be measured.
Interval time = (CM1n0 register value + 1) × TMENC1n count clock rate
Free-running cycle = 65,536 × TMENC1n count clock rate
compare register mode.
Remark
The CC1n0 and CC1n1 registers are capture/compare registers. Which of these registers
is used is specified by the CCR1n register.
Table 8-3. Capture Trigger Signal to 16-Bit Capture Register
Capture Register
CC1n0
CC1n1
User’s Manual U16543EJ4V0UD
Note
, INTCCn1
Note
) is output. Particularly in the case of a interval
Capture Trigger Signal
TCUD1n or TCLR1n
TCUD1n
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