M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 299

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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(1) Counter basic operation
This section explains the basic operation of the 16-bit counter. For details, refer to the description of the
operation in each mode.
Remark
(a) Counter start operation
(b) Clear operation
(c) Overflow operation
(d) Counter read operation during counting operation
• In external event count mode
• In modes other than the above
The 16-bit counter is cleared to 0000H when its value matches the value of the compare register and when
its value is captured. The counting operation from FFFFH to 0000H that takes place immediately after the
counter has started counting or when the counter overflows is not a clearing operation. Therefore, the
INTTQnCCa interrupt signal is not generated.
The 16-bit counter overflows when the counter counts up from FFFFH to 0000H in the free-running timer
mode or pulse width measurement mode. If the counter overflows, the TQnOPT0.TQnOVF bit is set to 1
and an interrupt request signal (INTTQnOV) is generated.
generated under the following conditions.
• Immediately after a counting operation has been started
• If the counter value matches the compare value FFFFH and is cleared
• When FFFFH is captured in the pulse width measurement mode and the counter counts up from FFFFH
Caution After the overflow interrupt request signal (INTTQnOV) has been generated, be sure to
The value of the 16-bit counter of TMQn can be read by using the TQnCNT register during the count
operation. When the TQnCTL0.TQnCE bit = 1, the value of the 16-bit counter can be read by reading the
TQ0CNT register. When the TQnCE bit = 0, the 16-bit counter is FFFFH and the TQnCNT register is
0000H.
to 0000H
When the TQ0CTL0.TQ0CE bit is set from 0 to 1, the 16-bit counter is set to 0000H.
After that, it counts up from 0001H to 0002H, 0003H, and so on, each time the valid edge of an external
event count input (EVTQ0) is detected.
The 16-bit counter of TMQn starts counting from the default value FFFFH in all modes.
It counts up from FFFFH to 0000H, 0001H, 0002H, 0003H, and so on.
n = 0, 1
a = 0 to 3
check that the overflow flag (TQnOVF bit) is set to 1.
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
User’s Manual U16543EJ4V0UD
Note that the INTTQnOV signal is not
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