M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 607

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

<R>
(2) CSIBn control register 1 (CBnCTL1)
CBnCTL1 is an 8-bit register that controls the CSIBn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution The CBnCTL1 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0.
CBnCTL1
(n = 0, 1)
After reset: 00H
Caution Set f
CBnCKS2
Communication
Communication
Communication
Communication
type 1
type 2
type 3
type 4
0
0
0
0
1
1
1
1
0
CHAPTER 15 CLOCKED SERIAL INTERFACE B (CSIB)
R/W
CBnCKS1
CBnCKP
0
0
0
1
1
0
0
1
1
0
0
1
1
CCLK
Address: CB0CTL1 FFFFFD01H, CB1CTL1 FFFFFD11H
CBnCKS0
User’s Manual U16543EJ4V0UD
CBnDAP
to 8 MHz or lower.
0
1
0
1
0
1
0
1
0
1
0
1
0
SOBn (output)
SOBn (output)
SOBn (output)
SOBn (output)
SIBn capture
SIBn capture
SIBn capture
SIBn capture
SCKBn (I/O)
SCKBn (I/O)
SCKBn (I/O)
SCKBn (I/O)
CBnCKP CBnDAP CBnCKS2 CBnCKS1 CBnCKS0
f
f
f
f
f
f
f
External clock (SCKBn)
XX
XX
XX
XX
XX
XX
XX
Communication clock (f
/4
/8
/16
/32
/64
/128
/256
reception timing in relation to SCKBn
Specification of data transmission/
D7
D7
D7
D7
D6
D6
D6
D6
D5
D5
D5
D5
CCLK
D4
D4
)
D4
D4
D3
D3
D3
D3
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Slave mode
D2
D2
D2
D2
Mode
D1
D1
D1
D1
D0
D0
D0
D0
605