M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 241

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
<R>
<2> TPmCCR0, TPmCCR1 register setting change flow
(1) Operation flow in one-shot pulse output mode
<1> Count operation start flow
Setting of TPmCCR0, TPmCCR1
External trigger input
INTTPmCC0 signal
INTTPmCC1 signal
TPmCCR0 register
TPmCCR1 register
(TPmCKS0 to TPmCKS2 bits)
TOPm1 pin output
Remark
(TIPk0 pin input)
Register initial setting
TPmCCR0 register,
16-bit counter
TPmCTL1 register,
TPmIOC0 register,
TPmCCR1 register
TPkIOC2 register,
TPmCTL0 register
TPmCE bit = 1
TPmCE bit
registers
START
FFFFH
0000H
Figure 6-30. Software Processing Flow in One-Shot Pulse Output Mode
V850E/IA3: m = 0, 2, k = 0, 2, a = 0, 1
V850E/IA4: m = 0, 2, 3, k = 0, 2, a = 0, 1
<1>
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
The TPmCKS0 to
TPmCKS2 bits can be
set at the same time
when counting has been
started (TPmCE bit = 1).
Trigger wait status
As rewriting the
TPmCCRa register
immediately forwards
to the CCRa buffer
register, rewriting
immediately after
the generation of the
INTTPmCC0 signal
is recommended.
Initial setting of these
registers is performed
before setting the
TPmCE bit to 1.
D
D
D
10
00
10
User’s Manual U16543EJ4V0UD
D
00
<2>
<3> Count operation stop flow
D
D
D
11
01
11
D
01
TPmCE bit = 0
STOP
<3>
Count operation is stopped
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