M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 461

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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10.4.4 Operation to rewrite register with transfer function
has a buffer register.
The following seven registers are provided with a transfer function and used to control a motor. Each of registers
• TQnCCR0: Register that specifies the cycle of the 16-bit counter (TMQ)
• TQnCCR1: Register that specifies the duty factor of TOQnT1 (U) and TOQnB1 (U)
• TQnCCR2: Register that specifies the duty factor of TOQnT2 (V) and TOQnB2 (V)
• TQnCCR3: Register that specifies the duty factor of TOQnT3 (W) and TOQnB3 (W)
• TQnOPT1: Register that specifies the culling of interrupts
• TPnCCR0: Register that specifies the A/D conversion start trigger generation timing (TMPn during tuning
• TPnCCR1: Register that specifies the A/D conversion start trigger generation timing (TMPn during tuning
The following three rewrite modes are provided in the registers with a transfer function.
• Anytime rewriting mode
• Batch rewrite mode (transfer mode)
• Intermittent batch rewrite mode (transfer culling mode)
This mode is specified by setting the TQnOPT0.TQnCMS bit to 1. The setting of the TQnOPT2.TQnRDE bit is
ignored.
In this mode, each compare register is updated independently, and the value of the compare register is updated
as soon as a new value is written to it.
This mode is set by clearing the TQnOPT0.TQnCMS bit to 0, the TQnOPT1.TQnID4 to TQnOPT1.TQnID0 bits to
00000, and the TQnOPT2.TQnRDE bit to 0.
When data is written to the TQnCCR1 register, the seven registers are transferred to the buffer register all at
once at the next transfer timing. Unless the TQnCCR1 register is rewritten, the transfer operation is not
performed even if the other six registers are rewritten.
The transfer timing is the timing of each crest (match between the 16-bit counter value and TQnCCR0 register
value) and valley (match between the 16-bit counter value and 0001H) regardless of the interrupt.
This mode is set by clearing the TQnOPT0.TQnCMS bit to 0 and setting the TQnOPT2.TQnRDE bit to 1.
When data is written to the TQnCCR1 register, the seven registers are transferred to the buffer register all at
once at the next transfer timing. Unless the TQnCCR1 register is rewritten, the transfer operation is not
performed even if the other six registers are rewritten.
If interrupt culling is specified by the TQnOPT1 register, the transfer timing is also culled as the interrupts are
culled, and the seven registers are transferred all at once at the culled timing of crest interrupt (match between
the 16-bit counter value and TQnCCR0 register value) or valley interrupt (match between the 16-bit counter value
and 0001H).
For details of the interrupt culling function, see 10.4.3 Interrupt culling function.
operation)
operation)
CHAPTER 10 MOTOR CONTROL FUNCTION
User’s Manual U16543EJ4V0UD
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