M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 714

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.4 IDLE Mode
18.4.1 Setting and operation status
mode.
peripheral functions stops.
retained. The CPU and other on-chip peripheral functions stop operating. However, the on-chip peripheral functions
that can operate with an external clock continue operating.
the on-chip peripheral functions. The clock generator and PLL do not stop, so the normal operation mode can be
restored without waiting for the oscillation stabilization time after the IDLE mode has been released, in the same
manner as when the HALT mode is released.
18.4.2 Releasing IDLE mode
INTP2 to INTP5, INTP7 pin input), unmasked internal interrupt request signal (CSIB-related interrupt request signal in
the slave mode) from the peripheral functions operable in the IDLE mode, or RESET pin input.
712
Unmasked maskable interrupt request
The IDLE mode is set by clearing (0) the PSMR.PSM0 bit and setting (1) the PSC.STB bit in the normal operation
In the IDLE mode, the clock generator and PLL continue operation but clock supply to the CPU and other on-chip
As a result, program execution stops and the contents of the internal RAM before the IDLE mode was set are
Table 18-5 shows the operation status in the IDLE mode.
The IDLE mode can reduce the power consumption more than the HALT mode because it stops the operation of
Caution Insert five or more NOP instructions after the instruction that stores data in the PSC register to
The IDLE mode is released by an unmasked external interrupt request signal (INTP0, INTP1 (V850E/IA4 only),
After the IDLE mode has been released, the normal operation mode is restored.
(1) Releasing IDLE mode by unmasked maskable interrupt request signal
The IDLE mode is released by an unmasked maskable interrupt request signal, regardless of the priority of the
interrupt request. If the IDLE mode is set in an interrupt servicing routine, however, an interrupt request that is
issued later is processed as follows.
Caution When PSC.INTM bit = 1, the IDLE mode cannot be released by the unmasked maskable
(a) If an interrupt request with a priority lower than or same as the interrupt request signal currently being
(b) If an interrupt request signal with a priority higher than that of the interrupt request signal currently being
serviced is generated, the IDLE mode is released, but the newly generated interrupt is not acknowledged.
The interrupt request signal itself is retained. Therefore, execution starts at the next instruction after the
IDLE instruction.
serviced is issued (including a non-maskable interrupt request signal), the IDLE mode is released and that
interrupt request signal is acknowledged. Therefore, execution branches to the handler address.
Release Source
set the IDLE mode.
Table 18-4. Operation After Releasing IDLE Mode by Interrupt Request Signal
interrupt request signal.
Execution branches to the handler
address or the next instruction is
executed
CHAPTER 18 STANDBY FUNCTION
User’s Manual U16543EJ4V0UD
Interrupt Enabled (EI) Status
The next instruction is executed
Interrupt Disabled (DI) Status