M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 271

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
<R>
<R>
later detected, the count value of the 16-bit counter is stored in the TPkCCRa register, the 16-bit counter is cleared to
0000H, and a capture interrupt request signal (INTTPkCCa) is generated.
interrupt request signal (INTTPkOV) is generated at the next count clock, and the counter is cleared to 0000H and
continues counting. At this time, the overflow flag (TPkOPT0.TPkOVF bit) is also set to 1. Clear the overflow flag to 0
by executing the CLR instruction via software.
When the TPkCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIPka pin is
The pulse width is calculated as follows.
If the valid edge is not input to the TIPnm pin even when the 16-bit counter counted up to FFFFH, an overflow
If the overflow flag is set to 1, the pulse width can be calculated as follows.
Remark
Pulse width = Captured value × Count clock cycle
Pulse width = (10000H × Number of times for which TPkOVF bit is set to 1 + Captured value) × Count clock cycle
INTTPkCCa signal
TPkCCRa register
Remark
INTTPkOV signal
k = 0, 2
a = 0, 1
TIPka pin input
16-bit counter
TPkOVF bit
TPkCE bit
FFFFH
0000H
k = 0, 2
a = 0, 1
Figure 6-42. Basic Timing in Pulse Width Measurement Mode
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
0000H
User’s Manual U16543EJ4V0UD
D
0
D
1
Cleared to 0 by
CLR instruction
D
2
D
3
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