M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 364

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

362
• Capture operation
When the TQ0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIQ0a pin is
detected, the count value of the 16-bit counter is stored in the TQ0CCRa register, and a capture interrupt request
signal (INTTQ0CCa) is generated.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTQ0OV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TQ0OVF bit) is also set to 1. Confirm that the overflow flag is set to 1
and then clear it to 0 by executing the CLR instruction via software.
Remark
INTTQ0CC0 signal
INTTQ0CC1 signal
INTTQ0CC2 signal
INTTQ0CC3 signal
TQ0CCR0 register
TQ0CCR1 register
TQ0CCR2 register
TQ0CCR3 register
INTTQ0OV signal
TIQ00 pin input
TIQ01 pin input
TIQ02 pin input
TIQ03 pin input
16-bit counter
Figure 7-35. Basic Timing in Free-Running Timer Mode (Capture Function)
TQ0OVF bit
TQ0CE bit
a = 0 to 3
FFFFH
0000H
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
0000
0000
0000
0000
D
20
D
00
D
30
User’s Manual U16543EJ4V0UD
D
10
D
Cleared to 0 by
CLR instruction
00
D
D
20
D
01
D
10
30
D
11
D
21
D
31
D
01
Cleared to 0 by
CLR instruction
D
11
D
12
D
D
D
21
02
31
D
22
D
32
D
D
CLR instruction
Cleared to 0 by
02
12
D
03
D
D
D
13
32
22
D
D
33
03
D
23
D
13
D
D
33
23