M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 341

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
(e) Generation timing of compare match interrupt request signal (INTTQ0CCb)
The timing of generation of the INTTQ0CCb signal in the external trigger pulse output mode differs from
the timing of INTTQ0CCb signals in other modes; the INTTQ0CCb signal is generated when the count
value of the 16-bit counter matches the value of the CCRb buffer register.
Count clock
− 2
− 1
16-bit counter
D
D
D
D
+ 1
D
+ 2
b
b
b
b
b
CCRb buffer register
D
b
Note
TOQ0b pin output
Note
INTTQ0CCb signal
Note Actually, the timing is delayed by one operating clock (f
).
XX
Remark
b = 1 to 3
Usually, the INTTQ0CCb signal is generated in synchronization with the next count up after the count
value of the 16-bit counter matches the value of the CCRb buffer register.
In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the
timing is changed to match the timing of changing the output signal of the TOQ0b pin.
339
User’s Manual U16543EJ4V0UD

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