M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 527

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(2) 4-buffer mode (4 buffers of software trigger continuous select)
Remark
(1) The ADA0CE bit = 1 (enable)
(2) The ANI02 pin is A/D converted
(3) The conversion result is stored in the ADA0CR0 register (9) The conversion result is stored in the ADA0CR3 register
(4) The ANI02 pin is A/D converted
(5) The conversion result is stored in the ADA0CR1 register (11) Return to (2)
(6) The ANI02 pin is A/D converted
In this mode, the voltage of one analog input pin (ANInm)
stored in the ADAnCRm register.
When the 4th A/D conversion ends, an A/Dn conversion end interrupt request signal (INTADn) is generated.
After the end of A/D conversion, the conversion is started again from the beginning, unless the
ADAnM0.ADAnCE bit is cleared to 0. It is not necessary to set (1) the ADAnM0.ADAnCE bit to restart A/D
conversion
Notes 1. Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used.
This mode is suitable for applications in which the average of the A/D conversion results of one analog input
pin is calculated.
Remark
Note Only the ANI00 and ANI01 pins can be used when A/D converter 0 of the V850E/IA3 is used.
ADA0M0
ANInm
ANInm
ANInm
ANInm
Analog Input Pin
This is an operation example with the following setting.
ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits = 00, ADA0M0.ADA0TMD bit = 0,
ADA0M2.ADA0BS bit = 1, ADA0S.ADA0S2 to ADA0S.ADA0S0 bits = 010
2. In the software trigger continuous select 4-buffer mode, the A/D conversion operation is not stopped
unless the ADAnM0.ADAnCE bit is cleared to 0. If the ADAnCRm register is not read before the
next A/D conversion ends, it is overwritten.
n = 0, 1
m = 0 to 3
Note 2
Note
Note
Note
Note
.
(4 Buffers of Software Trigger Continuous Select): V850E/IA4
ADAnCR0
ADAnCR1
ADAnCR2
ADAnCR3
Figure 12-12. Example of 4-Buffer Mode Operation
A/D Conversion Result Register
ANI00
ANI01
ANI02
ANI03
CHAPTER 12 A/D CONVERTERS 0 AND 1
(×4)
User’s Manual U16543EJ4V0UD
(7) The conversion result is stored in the ADA0CR2 register
(8) The ANI02 pin is A/D converted
(10) The INTAD0 interrupt request signal is generated
(12) To end the conversion, the ADA0CE bit = 0 (stop)
A/D converter 0
Note 1
is A/D converted four times and the results are
ADA0CR0
ADA0CR1
ADA0CR2
ADA0CR3
525