M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 503

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
(3) A/D converter n channel specification register (ADAnS) (n = 0, 1)
Remark
Note In the V850E/IA3, these can be set only when A/D converter 1 is used. They must not be set when A/D
Cautions 1. If the ADAnS register is written during A/D conversion (ADAnM0.ADAnEF bit = 1), the
The ADAnS register is an 8-bit register that specifies the analog input pin.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
converter 0 is used.
2. Be sure to clear bits 3 to 7 to “0”.
A/D conversion of the analog input pin is performed as follows in the scan mode.
• When ADAnS2 to ADAnS0 bits = 100
• When ADAnS2 to ADAnS0 bits = 101
• When ADAnS2 to ADAnS0 bits = 110
(n = 0, 1)
ANIn0 → ANIn1 → ANIn2
ANIn0 → ANIn1 → ANIn2
operational amplifier operation
ANIn0 → ANIn1 → ANIn2
operational amplifier operation → ANIn2 operational amplifier operation
ADAnS
operation is performed as follows in each mode.
• In software trigger mode
• In hardware trigger mode
After reset: 00H
A/D conversion is stopped and executed again from the beginning.
A/D conversion is stopped and the trigger standby state is restored again.
ADAnS2
0
0
0
0
1
1
1
1
0
ADAnS1
CHAPTER 12 A/D CONVERTERS 0 AND 1
R/W
0
0
0
1
1
0
0
1
1
Note
Note
Note
→ ANIn3
→ ANIn3
→ ANIn3
Address: ADA0S FFFFF202H, ADA1S FFFFF222H
User’s Manual U16543EJ4V0UD
ADAnS0
0
1
0
1
0
1
0
1
0
Note
Note
Note
ANIn0
ANIn1
ANIn2
ANIn3
ANIn0 + operational
amplifier operation
ANIn1 + operational
amplifier operation
ANIn2 + operational
amplifier operation
Setting prohibited
→ ANIn0 operational amplifier operation
→ ANIn0 operational amplifier operation → ANIn1
→ ANIn0 operational amplifier operation → ANIn1
0
Select mode
Note
Note
0
Note
ADAnS2 ADAnS1 ADAnS0
ANIn0
ANIn0, ANIn1
ANIn0 to ANIn2
ANIn0 to ANIn3
ANIn0 →
(ANIn0 + operational
amplifier operation)
ANIn0 →
(ANIn1 + operational
amplifier operation)
ANIn0 →
(ANIn2 + operational
amplifier operation)
Setting prohibited
Scan mode
Note
Note
Note
501

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