M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 53

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(1) Interrupt status saving registers (EIPC, EIPSW)
EIPSW
EIPC
There are two interrupt status saving registers, EIPC and EIPSW.
Upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (PC)
are saved to EIPC and the contents of the program status word (PSW) are saved to EIPSW (upon occurrence
of a non-maskable interrupt (NMI), the contents are saved to the NMI status saving registers (FEPC,
FEPSW)).
The address of the next instruction following the instruction executed when a software exception or maskable
interrupt occurs is saved to EIPC, except for some instructions (see 17.9 Periods in Which CPU Does Not
Acknowledge Interrupts).
The current PSW contents are saved to EIPSW.
Since there is only one set of interrupt status saving registers, the contents of these registers must be saved
by the program when multiple interrupt servicing is enabled.
Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved (fixed to 0) for future function expansion.
When the RETI instruction is executed, the values in EIPC and EIPSW are restored to the PC and PSW,
respectively.
31
31
0
0
0
0
0 0 0 0
0 0 0 0
26 25
0
0
0 0 0 0
CHAPTER 3 CPU FUNCTION
User’s Manual U16543EJ4V0UD
0
0
0 0 0 0
(PC contents saved)
0
0
0 0 0 0
8
(PSW contents saved)
7
0
0
(x: Undefined)
(x: Undefined)
000000xxH
0xxxxxxxH
After reset
After reset
51