M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 498

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

496
(4) Array
(5) Successive approximation register (SAR)
(6) A/Dn conversion result registers 0 to 3 (ADAnCR0 to ADAnCR3), A/Dn conversion result registers 0H
(7) A/Dn conversion result registers 4 to 7 (ADAnCR4 to ADAnCR7), A/Dn conversion result registers 4H
(8) A/D converter n mode register 0 (ADAnM0) (n = 0, 1)
(9) A/D converter n mode register 1 (ADAnM1) (n = 0, 1)
The voltage tap of the array and the analog input voltage are compared and bit 8 of the SAR is manipulated
according to the result of the comparison.
Comparison is continued like this to bit 0 of the SAR.
The array generates the comparison voltage input from an analog input pin (ANIn0 to ANIn3 (ANI00 and ANI01
only for A/D converter 0 of the V850E/IA3)) (n = 0, 1).
The SAR is a 10-bit register that sets voltage tap data whose values from the array match the voltage values of
the analog input pins, 1 bit at a time starting from the most significant bit (MSB).
If data is set in the SAR all the way to the least significant bit (LSB) (end of A/D conversion), the contents of
the SAR (conversion results) are held in A/Dn conversion result registers 0 to 3 (ADAnCR0 to ADAnCR3) (n =
0, 1). If the operational amplifier for input level amplification is used, however, the conversion result is held by
the ADAnCR4 to ADAnCR7 registers. When all the specified A/D conversion operations have ended, an A/Dn
conversion end interrupt request signal (INTADn) is generated.
to 3H (ADAnCR0H to ADAnCR3H) (n = 0, 1)
The ADAnCR0 to ADAnCR3 and ADAnCR0H to ADAnCR3H registers are registers that hold the A/D
conversion results. Each time A/D conversion ends, the conversion result is loaded from the successive
approximation register (SAR) and stored in the higher 10 bits of the ADAnCR0 to ADAnCR3 registers. The
lower 6 bits of these registers are always 0 when read.
The higher 8 bits of the result of A/D conversion are read from the ADAnCR0H to ADAnCR3H registers. To
read the result of A/D conversion in 16-bit units, specify the ADAnCR0 to ADAnCR3 registers. To read the
higher 8 bits, specify the ADAnCR0H to ADAnCR3H registers.
to 7H (ADAnCR4H to ADAnCR7H) (n = 0, 1)
The ADAnCR4 to ADAnCR7 and ADAnCR4H to ADAnCR7H registers are registers that hold the A/D
conversion results.
amplification is used. Each time A/D conversion ends, the conversion result is loaded from the successive
approximation register (SAR) and stored in the higher 10 bits of the ADAnCR4 to ADAnCR7 registers. The
lower 6 bits of these registers are always 0 when read.
The higher 8 bits of the result of A/D conversion are read from the ADAnCR4H to ADAnCR7H registers. To
read the result of A/D conversion in 16-bit units, specify the ADAnCR4 to ADAnCR7 registers. To read the
higher 8 bits, specify the ADAnCR4H to ADAnCR7H registers.
This register is used to specify the operation mode and controls the conversion operation.
This register is used to set the number of conversion clocks of the analog input to be A/D converted.
Analog input voltage ≥ Voltage tap of array: Bit 8 = 1
Analog input voltage ≤ Voltage tap of array: Bit 8 = 0
These registers can be used only when the operational amplifier for input level
CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U16543EJ4V0UD