M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 306

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.6.1
TQnCCR0 register if the TQnCTL0.TQnCE bit is set to 1. A PWM waveform with a duty factor of 50% whose half
cycle is equal to the interval can be output from the TOQn0 pin (the TOQ10 pin is provided in the V850E/IA4 only).
TQnCCR1 to TQnCCR3 registers is transferred to the CCR1 to CCR3 buffer registers and, when the count value of
the 16-bit counter matches the value of the CCR1 to CCR3 buffer registers, compare match interrupt request signals
(INTTQnCC1 to INTTQnCC3) are generated. In addition, a PWM waveform with a duty factor of 50%, which is
inverted when the INTTQ0CC1 to INTTQ0CC3 signals are generated, can be output from the TOQ01 to TOQ03 pins.
304
In the interval timer mode, an interrupt request signal (INTTQnCC0) is generated at the interval set by the
The TQnCCR1 to TQnCCR3 registers are not used in the interval timer mode. However, the set value of the
The value of the TQnCCR1 to TQnCCR3 registers can be rewritten even while the timer is operating.
Interval timer mode (TQnMD2 to TQnMD0 = 000)
TOQn0 pin
Count clock
selection
INTTQnCC0 signal
Note The TOQ10 pin is provided only in the V850E/IA4.
Remark
TQnCCR0 register
Note The TOQ10 pin is provided only in the V850E/IA4.
Remark
16-bit counter
TQnCE bit
Note
FFFFH
n = 0, 1
0000H
n = 0, 1
output
TQnCE bit
Figure 7-8. Basic Timing of Operation in Interval Timer Mode
CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
Interval (D
Figure 7-7. Interval Timer Configuration
User’s Manual U16543EJ4V0UD
D
0
0
+ 1) Interval (D
CCR0 buffer register
TQnCCR0 register
16-bit counter
Clear
Match signal
D
0
0
+ 1) Interval (D
D
0
D
0
controller
0
Output
+ 1) Interval (D
INTTQnCC0 signal
D
0
0
+ 1)
TOQn0 pin
Note