M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 207

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
<R>
<R>
(1) Interval timer mode operation flow
<1> Count operation start flow
Note Enable setting of the TPkEES1 and TPkEES0 bits only when timer output (TOPk1) is used.
Remark
INTTPnCC0 signal
TPnCCR0 register
TOP00 pin output
(TPnCKS0 to TPnCKS2 bits)
In this case, set the TPkCCR0 and TPkCCR1 registers to the same value.
16-bit counter
Register initial setting
TPkIOC2 register
V850E/IA3: n = 0 to 3, m = 0, 2, k = 0, 2
V850E/IA4: n = 0 to 3, m = 0, 2, 3, k = 0, 2
TPmIOC0 register,
TPnCTL1 register,
TPnCCR0 register
TPnCE bit
TPnCTL0 register
Figure 6-12. Software Processing Flow in Interval Timer Mode (1/2)
TPnCE bit = 1
FFFFH
0000H
START
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
Note
,
<1>
User’s Manual U16543EJ4V0UD
D
Initial setting of these registers is performed
before setting the TPnCE bit to 1.
The TPnCKS0 to TPnCKS2 bits can be
set at the same time when counting has
been started (TPnCE bit = 1).
0
D
0
D
0
D
0
<2>
205

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