M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 597

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(7) Allowable baud rate range during reception
The baud rate error range at the destination that is allowable during reception is shown below.
Caution The baud rate error during reception must be set within the allowable error range using the
As shown in Figure 14-11, the receive data latch timing is determined by the counter set using the UAnCTL2
register following start bit detection. The transmit data can be normally received if up to the last data (stop bit)
can be received in time for this latch timing.
When this is applied to 11-bit reception, the following is the theoretical result.
Remark
FL = (Brate)
Minimum allowable transfer rate: FLmin = 11 × FL −
transfer rate
transfer rate
transfer rate
Maximum
Brate: UARTAn baud rate (n = 0, 1)
k:
FL:
Latch timing margin: 2 clocks
allowable
allowable
Minimum
UARTAn
following equation.
n = 0, 1
Setting value of UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (n = 0, 1)
1-bit data length
−
1
CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Figure 14-11. Allowable Baud Rate Range During Reception
Latch timing
Start bit
Start bit
Start bit
Bit 0
Bit 0
FL
Bit 0
User’s Manual U16543EJ4V0UD
Bit 1
Bit 1
Bit 1
1 data frame (11 × FL)
FLmin
k − 2
2k
FLmax
× FL =
Bit 7
Bit 7
Bit 7
21k + 2
Parity bit
2k
Parity bit
Parity bit
FL
Stop bit
Stop bit
Stop bit
595