M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 412

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/GENERAL-PURPOSE TIMER (TIMER ENC1n)
(4) Operation in UDC mode B
(a) Basic operation
(b) Compare function
(c) Capture function
The operations at the next count clock after the count value of TMENC1n and the CM1n0 register set
value match when TMENC1n is in UDC mode B are as follows.
• In case of count up operation:
• In case of count down operation: The TMENC1n count value is decremented (−1).
The operations at the next count clock after the count value of TMENC1n and the CM1n1 register set
value match when TMENC1n is in UDC mode B are as follows.
• In case of count up operation:
• In case of count down operation: TMENC1n is cleared (0000H) and the INTCMn1 interrupt request
TMENC1n connects two compare register (CM1n0, CM1n1) channels and two capture/compare register
(CC1n0, CC1n1) channels.
When the TMENC1n count value and the set value of one of the compare registers match, a match
interrupt request signal (INTCMn0 (only during count up operation), INTCMn1 (only during count down
operation), INTCCn0
Note This match interrupt request signal is generated when the CC1n0 and CC1n1 registers are set to
TMENC1n connects two capture/compare register (CC1n0, CC1n1) channels.
When the CC1n0 and CC1n1 registers are set to the capture register mode, the value of TMENC1n is
captured in synchronization with the corresponding capture trigger signal.
request signal (INTCCn0, INTCCn1) is generated upon detection of the valid edge.
CM1n0 register set value
CM1n1 register set value
TMENC1n count value
the compare register mode.
Figure 8-11. Example of TMENC1n Operation in UDC Mode
Note
, INTCCn1
Clear
Note
User’s Manual U16543EJ4V0UD
TMENC1n is cleared (0000H) and the INTCMn0 interrupt request
signal is generated.
The TMENC1n count value is incremented (+1).
signal is generated.
) is output.
TMENC1n not cleared
down following match
if count clock counts
Clear
TMENC1n not cleared
if count clock counts
up following match
Also, a capture interrupt