M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 431

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

<R>
(3) TMQn option register 2 (TQnOPT2)
Note V850E/IA4 only
Cautions 1. When using interrupt culling (the TQnOPT1.TQnID4 to TQnOPT1.TQnID0 bits are set to
The TQnOPT2 register is an 8-bit register that controls the timer Q option function.
This register can be rewritten when the TQnCTL0.TQnCE bit is 1. However, rewriting the TQnDTM bit is
prohibited when the TQnCE bit is 1. The same value can be rewritten.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
2. To generate the dead-time period, set the TQnDTC register to 1 or greater.
V850E/IA3
V850E/IA4
m = 1 to 3
m = 1 to 3
TQnOPT2
n = 0, 1
other than 00000), be sure to set the TQnRDE bit to 1.
Therefore, the interrupt and transfer are generated at the same timing. The interrupt and
transfer cannot be set separately. If the interrupt and transfer are set separately (TQnRDE
bit = 0), transfer is not performed normally.
When the operation is stopped (TQnCTL0.TQnCE bit = 0), the dead-time period is not
generated and the output level of the TOQnT1 to TOQnT3 pins and TOQnB1 to TOQnB3
pins will be in the initial status. For the system protection, therefore, before operation is
stopped, set the TOQnT1 to TOQnT3 and TOQnB1 to TOQnB3 pins to the high impedance
state, or set the output level of pins and switch them to the port mode.
If a dead time period is not needed, set the TQnDTC register to 0.
n = 0
After reset: 00H
TQnRDE
TQnRDE
TQnDTM
Rewriting the TQnDTM bit is disabled during timer operation. If it is rewritten by
mistake, stop the timer operation by clearing the TQnCE bit to 0, and re-set the
TQnDTM bit.
<7>
0
1
0
1
CHAPTER 10 MOTOR CONTROL FUNCTION
TQnDTM TQnATM03 TQnATM02 TQnAT03 TQnAT02 TQnAT01 TQnAT00
Dead-time counter counts up normally and, if TOQnm output of TMQn is
at a narrow interval (TOQnm output width < dead-time width), the dead-
time counter is cleared and counts up again.
Dead-time counter counts up normally and, if TOQnm output of TMQn is
at a narrow interval (TOQnm output width < dead-time width), the dead-
time counter counts down and the dead-time control width is automatically
narrowed.
Do not cull transfer (transfer timing is generated every time at crest
and valley).
Cull transfer at the same interval as interrupt culling set by the TQnOPT1
register.
R/W
<6>
User’s Manual U16543EJ4V0UD
Address: TQ0OPT2 FFFFF5E1H, TQ1OPT2 FFFFF621H
<5>
Dead-time counter operation mode selection
<4>
Transfer culling enable
<3>
<2>
<1>
<0>
Note
(1/2)
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