M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 706

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
17.8 Interrupt Response Time of CPU
signals successively, input the next interrupt request signal at least 4 clocks after the preceding interrupt.
704
Instruction (start instruction of interrupt servicing routine)
Except the following cases, the interrupt response time of the CPU is 4 clocks minimum. To input interrupt request
• In IDLE/STOP mode
• When interrupt request non-sampling instructions are successively executed (see 17.9 Periods in Which CPU
• When an on-chip peripheral I/O register is accessed
Remark
Notes 1. V850E/IA4 only
Maximum
Minimum
Does Not Acknowledge Interrupts.)
2. For details, see 4.6 (1) External interrupt noise elimination control register (INTPNRC).
INT1 to INT4: Interrupt acknowledgment processing
IFX:
IDX:
Interrupt latency time (internal system clock)
Figure 17-14. Pipeline Operation at Interrupt Request Acknowledgment (Outline)
interrupt
Internal
4
8
Interrupt acknowledgment operation
INTP0, INTP1
Analog delay time
Analog delay time
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
INTP2 to INTP5,
Invalid instruction fetch
Invalid instruction decode
INTP7
4 +
8 +
External interrupt
Interrupt request
Note 1
Internal clock
Instruction 1
Instruction 2
,
User’s Manual U16543EJ4V0UD
Digital noise filter
Digital noise filter
4 + Note 2 +
8 + Note 2 +
INTP6
IF
IFX
IF
The following cases are exceptions.
• In IDLE/STOP mode
• Two or more interrupt request non-sample
• Access to on-chip peripheral I/O register
instructions are executed in succession
IFX
IF
INT1 INT2 INT3 INT4
IFX
ID
4 system clocks
IDX
EX
Conditions
DF
WB
IF
IF
IF
ID

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