M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 716

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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18.5 STOP Mode
18.5.1 Setting and operation status
mode.
functions is stopped.
are retained. The CPU and other on-chip peripheral functions stop operating. However, the on-chip peripheral
functions that can operate with an external clock continue operating.
the IDLE mode. When the external clock is not used, the power consumption can be minimized with only leakage
current flowing.
18.5.2 Releasing STOP mode
INTP2 to INTP5, INTP7 pin input), unmasked internal interrupt request signal (CSIB-related interrupt signal in the
slave mode) from the peripheral functions operable in the STOP mode, or RESET pin input.
time has been secured.
714
Unmasked maskable interrupt request
The STOP mode is set by setting (1) the PSMR.PSM0 bit and setting (1) the PSC.STB bit in the normal operation
In the STOP mode, the clock generator stops operation. Clock supply to the CPU and the on-chip peripheral
As a result, program execution is stopped, and the contents of the internal RAM before the STOP mode was set
Table 18-7 shows the operation status in the STOP mode.
Because the STOP stops operation of the clock generator, it reduces the power consumption to a level lower than
Caution Insert five or more NOP instructions after the instruction that stores data in the PSC register to
The STOP mode is released by an unmasked external interrupt request signal (INTP0, INTP1 (V850E/IA4 only),
After the STOP mode has been released, the normal operation mode is restored after the oscillation stabilization
(1) Releasing STOP mode by unmasked maskable interrupt request signal
The STOP mode is released by an unmasked maskable interrupt request signal, regardless of the priority of
the interrupt request. If the STOP mode is set in an interrupt servicing routine, however, an interrupt request
that is issued later is serviced as follows.
Caution When PSC.INTM bit = 1, the IDLE mode cannot be released by the unmasked maskable
(a) If an interrupt request with a priority lower than or same as the interrupt request currently being serviced is
(b) If an interrupt request with a priority higher than that of the interrupt request currently being serviced is
generated, the STOP mode is released, but the newly generated interrupt is not acknowledged. The
interrupt request itself is retained. Therefore, execution starts at the next instruction after the STOP
instruction.
issued, the STOP mode is released and that interrupt request is acknowledged. Therefore, execution
branches to the handler address.
Release Source
set the STOP mode.
Table 18-6. Operation After Releasing STOP Mode by Interrupt Request Signal
interrupt request signal.
Execution branches to the handler
address or the next instruction is
executed after securing oscillation
stabilization time
CHAPTER 18 STANDBY FUNCTION
User’s Manual U16543EJ4V0UD
Interrupt Enabled (EI) Status
The next instruction is executed after
securing oscillation stabilization time
Interrupt Disabled (DI) Status