M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 399

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CHAPTER 8 16-BIT 2-PHASE ENCODER INPUT UP/DOWN COUNTER/GENERAL-PURPOSE TIMER (TIMER ENC1n)
(6) Status register 1n (STATUS1n)
Note V850E/IA4 only
Operation Mode
(b) UDC mode (TUM1n.CMDn bit = 1)
The STATUS1n register indicates the operating status of TMENC1n.
This register is read-only in 8-bit or 1-bit units.
Reset sets this register to 00H.
Mode 1
Mode 2
Mode 3
Mode 4
The TMENC1n count triggers in the UDC mode are as follows.
V850E/IA3
V850E/IA4
STATUS1n
n = 0, 1
n = 0
After reset: 00H
Count down when TCUD1n = high level
Count up when TCUD1n = low level
Count up upon detection of valid edge of TIUD1n input
Count up upon detection of valid edge of TIUD1n input when TCUD1n = high level
Count down upon detection of valid edge of TIUD1n input when TCUD1n = low level
Automatic judgment upon detection of both edges of TIUD1n input and both edges of TCUD1n input
Count down upon detection of valid edge of TCUD1n input
TM1UDFn
TM1OVFn
TM1UBDn
The TM1UDFn bit is cleared (0) upon completion of a read access to the STATUS1n
register from the CPU.
The TM1OVFn bit is cleared (0) upon completion of a read access to the STATUS1n
register from the CPU.
The state of the TM1UBDn bit differs according to the mode as follows.
• The TM1UBDn bit is fixed to 0 in general-purpose timer mode (TUM1n.CMDn
• The TM1UBDn bit indicates the TMENC1n count up/down status in UDC mode
bit = 0).
(TUM1n.CMDn bit = 1).
0
1
0
1
0
1
7
0
No TMENC1n count underflow
TMENC1n count underflow
No TMENC1n count overflow
TMENC1n count overflow
TMENC1n count up in progress
TMENC1n count down in progress
R
6
0
User’s Manual U16543EJ4V0UD
Address: STATUS10 FFFFF58FH, STATUS11 FFFFF5AFH
5
0
TMENC1n count up/down operation status
TMENC1n underflow flag
TMENC1n overflow flag
4
0
TMENC1n Operation
3
0
TM1UDFn TM1OVFn TM1UBDn
<2>
<1>
<0>
Note
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