M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 215

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
<R>
6.6.2
TPkCTL0.TPkCE bit is set to 1, and an interrupt request signal (INTTPkCC0) is generated each time the number of
edges set by the TPkCCR0 register have been counted. The TOP00 and TOPk1 pins cannot be used. When using
the TOPk1 pin in the external event count input mode, set the TPkCTL1.TPkEEE bit to 1 in the interval timer mode
(see 6.6.1 (3) Operation by external event count input (TIPk0)).
TIPk0 pin
(external event
count input)
This mode is valid only in TMP0 and TMP2.
In the external event count mode, the valid edge of the external event count input (TIPk0) is counted when the
The TPkCCR1 register is not used in the external event count mode.
Caution In the external event count mode, the TPkCCR0 and TPkCCR1 registers must not be cleared to
External event count mode (TPkMD2 to TPkMD0 bits = 001)
Remark
0000H.
k = 0, 2
Edge
detector
Figure 6-16. Configuration in External Event Count Mode
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
TPkCE bit
User’s Manual U16543EJ4V0UD
CCR0 buffer register
TPkCCR0 register
16-bit counter
Clear
Match signal
INTTPkCC0 signal
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