M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 224

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M-V850E-IA4

Manufacturer Part Number
M-V850E-IA4
Description
KIT EVAL V850E IA4 UPD70F3186
Manufacturer
Renesas Electronics America
Datasheets

Specifications of M-V850E-IA4

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
<R>
6.6.3
TPmCTL0.TPmCE bit is set to 1. When the valid edge of an external trigger input (TIPk0) is detected, 16-bit
timer/event counter P starts counting, and outputs a PWM waveform from the TOPm1 pin.
a software trigger, a PWM waveform with a duty factor of 50% that has the set value of the TPmCCR0 register + 1 as
half its cycle can also be output from the TOP00 pin.
222
This mode is valid only in TMP0, TMP2, and TMP3 (V850E/IA4 only) (software trigger only for TMP3).
In the external trigger pulse output mode, 16-bit timer/event counter P waits for a trigger when the
Pulses can also be output by generating a software trigger instead of using the external trigger input. When using
(external trigger input)
External trigger pulse output mode (TPmMD2 to TPmMD0 bits = 010)
Note Because the external trigger input pin (TIP00) and timer output pin (TOP00) function alternately,
Caution In the external trigger pulse output mode, select the internal clock as the count clock
Remark
TIPk0 pin
two functions cannot be used at the same time.
Note
(by clearing the TPkCTL1.TPkEEE bit to 0).
V850E/IA3: m = 0, 2, k = 0, 2
V850E/IA4: m = 0, 2, 3, k = 0, 2
Figure 6-23. Configuration in External Trigger Pulse Output Mode
Software trigger
selection
generation
Count
clock
detector
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
Edge
TPmCE bit
User’s Manual U16543EJ4V0UD
control
Count
start
CCR1 buffer register
CCR0 buffer register
TPmCCR1 register
TPmCCR0 register
16-bit counter
Match signal
Match signal
Clear
Transfer
Transfer
S
R
controller
controller
Output
(RS-FF)
Output
INTTPmCC1 signal
INTTPmCC0 signal
TOPm1 pin
TOP00 pin
Note

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