M-V850E-IA4 Renesas Electronics America, M-V850E-IA4 Datasheet - Page 830

• Manufacturer Part Number: M-V850E-IA4
• Description: KIT EVAL V850E IA4 UPD70F3186
• Manufacturer: Renesas Electronics America

Specifications of M-V850E-IA4

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

D.2 Revision History up to Previous Edition
each edition in which the revision was applied.
828
2nd edition
The following table shows the revision history up to this edition. The “Applied to:” column indicates the chapters of
Edition
Addition of
Modification of pin configuration of pin 20 in 1.2.4 Pin configuration (V850E/IA3)
Modification of description in 2.2 Pin I/O Circuits and Recommended Connection of
Unused Pins
Modification of description in 2.3 Pin I/O Circuits
Addition and modification of Note 2 in Table 3-2 System Register Numbers
Addition of 3.2.2 (1) Interrupt status saving registers (EIPC, EIPSW), (2) NMI status
saving registers (FEPC, FEPSW), (5) CALLT execution status saving registers
(CTPC, CTPSW), (6) Exception/debug trap status saving registers (DBPC, DBPSW),
and (7) CALLT base pointer (CTBP)
Addition of Cautions and Remark in 3.5.4 (2) (c) Internal memory size switching
register (IMS)
Addition of Note in 3.4.7 On-chip peripheral I/O registers
Addition of Caution in 3.4.9 System wait control register (VSWC)
Modification of description in 3.4.10 Cautions
Addition of 4.3 Port Configuration
Modification of Figure 4-22 Block Diagram of P50 Pin
Addition of 4.5 Port Register Settings When Alternate Function Is Used
Modification of Notes in Table 4-16 Noise Eliminator
Modification of description in 4.7 Cautions
Addition and modification of Cautions in 5.3 (3) Power save control register (PSC)
Modification of CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
Modification of CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
Addition of Caution in 8.2 Features
Modification of description on Mode 3 in Table 8-4 List of Count Operations in UDC
Mode
Addition of description to 9.2 (2) TMM0 compare register 0 (TM0CMP0)
Modification of description in 9.3 (1) TMM0 control register 0 (TM0CTL0)
Modification of 9.4 Operation
μ
PD703186
APPENDIX D REVISION HISTORY
User’s Manual U16543EJ4V0UD
Description
Throughout
CHAPTER 1
INTRODUCTION
CHAPTER 2
PIN FUNCTIONS
CHAPTER 3
CPU FUNCTION
CHAPTER 4
PORT FUNCTIONS
CHAPTER 5
CLOCK
GENERATOR
CHAPTER 6
16-BIT
TIMER/EVENT
COUNTER P (TMP)
CHAPTER 7
16-BIT
TIMER/EVENT
COUNTER Q (TMQ)
CHAPTER 8
16-BIT 2-PHASE
ENCODER INPUT
UP/DOWN
COUNTER/
GENERAL-
PURPOSE TIMER
(TIMER ENC1n)
CHAPTER 9
16-BIT INTERVAL
TIMER M (TMM)
Applied to:
(1/6)