tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 96
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tmp19a61f10xbg
Manufacturer Part Number
tmp19a61f10xbg
Description
32-bit Tx System Risc Tx19 Family
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP19A61F10XBG.pdf
(575 pages)
Available stocks
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Part Number:
TMP19A61F10XBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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7.2
The port 0 is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in
units of bits. Outputs can be set by using the control register P0CR. A reset allows all bits of P0CR to be cleared
to "0" and the port 0 to be put in output disable mode.
Besides the general-purpose input/output function, the port 0 performs other functions: D0 through D7 function
as a data bus and AD0 through AD7 function as an address data bus. When external memory is accessed, all
bits of P0FC1 are set to "1."
If the BUSMD pin is set to "L" level, the port 0 is put in separate bus mode (D0 to D7). If it is set to "H" level, the
port 0 is put in multiplexed mode (AD0 to AD7).
Port 0 (P00~P07)
D0~D7
(Output latch)
P0 read
(Direction
(Function
P0FC1
P0CR
control)
control)
STOP/RESET
P0
Drive disable
TMP19A61(rev1.0) 7-95
Fig. 7.1 Port 0 (P00~P07)
Address/ data
Output enable
D0~D7/
AD0~AD7 1
External bus opening
0
1
0
P0 read
External read
TMP19A61
Port 0
P00~P07
(D0~D7)
(AD0~AD7)
RESET
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