tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 389

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Receive data
read timing
Transmit data
write timing
(HINTTX0 interrupt request)
(HINTRX0 interrupt request)
HSCLK0 input
HRXD0
HTXD0
In the HSCLK input mode with HSC0MOD2 <WBUF> set to "0" and the transmit
double buffers are disabled (double buffering is always enabled for the receive side),
8-bit data written in the transmit buffer is output from the HTXD0 pin and 8 bits of data
is shifted into the receive buffer when the HSCLK input becomes active. The HINTTX0
interrupt is generated upon completion of data transmission and the HINTRX0
interrupt is generated at the instant the received data is moved from Receive Buffer 1
to Receive Buffer 2. Note that transmit data must be written into the transmit buffer
before the HSCLK input for the next frame (data must be written before the point A). As
double buffering is enabled for data reception, data must be read before the
completion of the next frame data reception.
If HSC0MOD2 <WBUF> = "1" and double buffering is enabled for both transmission
and reception, the interrupt HINTRX0 is generated at the timing Transmit Buffer 2 data
is moved to Transmit Buffer 1 after completing data transmission from Transmit Buffer
1. At the same time, the 8 bits of data received is shifted to Receive Buffer 1, moved to
Receive Buffer 2, and the HINTRX0 interrupt is generated. Upon the HSCLK input for
the next frame, transmission from Transmit Buffer 1 (in which data has been moved
from Transmit Buffer 2) is started while receive data is shifted into Receive Buffer 1
simultaneously. If data in Receive Buffer 2 has not been read when the last bit of the
frame is received, an overrun error occurs. Similarly, if there is no data written to
Transmit Buffer 2 when HSCLK for the next frame is input, an under-run error occurs.
HSCLK input mode
bit 0
bit 0
<WBUF> ＝ ”0”(if double buffering is disabled)
bit 1
bit 1
TMP19A61(rev. 1.0) 14-388
bit 5
bit 5
bit 6
bit 6
bit 7
bit 7
A
TMP19A61
bit 0
bit 0
bit 1
bit 1