tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 366

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Data write timing to
transmit buffer or shift
register
(Note)
HTXDCLK
If the H CTS signal is set to "H" during transmission, the next data transmission is
suspended after the current transmission is completed.
Data transmission starts on the first falling edge of the HTXDCLK clock after H CTS is
set to "L".
HSIOCLK
Handshake function
prevented. This function can be enabled or disabled by HSC0MOD0 <CTSE>.
completed but the next data transmission is suspended until the H
"L" level. However in this case, the HINTTX0 interrupt is generated, the next transmit data is
requested to the CPU, data is written to the transmit buffer, and it waits until it is ready to
transmit data.
Although no H RTS pin is provided, a handshake control function can be easily
implemented by assigning a port for the H RTS function. By setting the port to "H" level
upon completion of data reception (in the receive interrupt routine), the transmit side can be
requested to suspend data transmission.
The H CTS pin enables frame by frame data transmission so that overrun errors can be
When the H
H
HTXD
CTS
Transmit side
Transmission is
suspended during
this period
CTS pin is set to the "H" level, the current data transmission can be
Fig. 14-7 H CTS (Clear to Transmit) Signal Timing
0
H CTS
HTXD
13
Fig. 14-6 Handshake Function
TMP19A61(rev 1.0)14-365
14
15
16
1
start bit
2
3
HRXD
H RTS (Any port)
Receive side
14
15
CTS pin returns to the
TMP19A61
16
0
1
bit 0
2
3