tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 326

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Data write timing to transmit
buffer or shift register
(Note) (1) If the CTS signal is set to “H” during transmission, the next data transmission is
TXDCLK
•
prevented. This function can be enabled or disabled by SC0MOD0 <CTSE>.
When the CTS pin is set to the “H” level, the current data transmission can be completed
but the next data transmission is suspended until the CTS pin returns to the “L” level.
However in this case, the INTTX0 interrupt is generated, the next transmit data is requested
to the CPU, data is written to the transmit buffer, and it waits until it is ready to transmit data.
Although no RTS pin is provided, a handshake control function can be easily implemented
by assigning a port for the RTS function. By setting the port to “H” level upon completion of
data reception (in the receive interrupt routine), the transmit side can be requested to
suspend data transmission.
(2) Data transmission starts on the first falling edge of the TXDCLK clock after CTS
is set to “L.”
suspended after the current transmission is completed.
SIOCLK
The CTS pin enables frame by frame data transmission so that overrun errors can be
CTS
TXD
Handshake function
Fig. 13.3.10.2 CTS (Clear to Transmit) Signal Timing
(1)
Transmit side
Transmission is
suspended during
this period.
Fig. 13.3.10.1 Handshake Function
13
CTS
TXD
TMP19A61 (rev1.0)-13-325
14
(2)
15
16
1
start bit
2
3
RXD
RTS (Any port)
Receive side
14
15
TMP19A61
16
1
bit 0
2
3