tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 522

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

7) Automatic programming of protection bits
8) Automatic erasing of protection bits
failed, the flash memory is locked in the mode and will not return to the read mode. In this
case, use the reset command or hardware reset to reset the flash memory or the device.
This device is implemented with four protection bits. The protection bits can be individually
set in the automatic programming. The applicable protection bit is specified in the seventh
bus write cycle. By automatically programming the protection bits, write and/or erase
functions can be inhibited (for protection) individually for each block. The protection status of
each block can be checked by the FLCS <BLPRO 3:0> register to be described later. This
status of the automatic programming operation to set protection bits can be checked by
monitoring FLCS <RDY/BSY> (See Table 22.16). Any new command sequence is not
accepted while automatic programming is in progress to program the protection bits. If it is
desired to stop the programming operation, use the hardware reset function. In this case, it
is necessary to perform the programming operation again because the protection bits may
not have been correctly programmed. If all the protection bits have been programmed, the
flash memory cannot be read from any area outside the flash memory such as the internal
RAM. In this condition, the FLCS <BLPRO 3:0> bits are set to "0 x F" indicating that it is in
the protected state (See Table 22.6). After this, no command writing can be performed.
Different results will be obtained when the automatic protection bit erase command is
executed depending on the status of the protection bits. It depends on the status of FLCS
<BLPRO 3:0> before the command execution whether it is set to "0 x F" or to any other
values. Be sure to check the value of FLCS <BLPRO 3:0> before executing the automatic
protection bit erase command.
・When FLCS <BLPRO 3:0> is set to "0 x F" (all the protection bits are programmed):
・When FLCS <BLPRO 3:0> is other than "0 x F" (not all the protection bits are
programmed):
The protection condition can be canceled by the automatic protection bit erase operation.
With this device, protection bits can be erased handling two bits at a time. The target bits are
specified in the seventh bus write cycle and when the command is completed, the device is
When the automatic protection bit erase command is command written, the flash memory is
automatically initialized within the device. When the seventh bus write cycle is completed,
the entire area of the flash memory data cells is erased and then the protection bits are
erased. This operation can be checked by monitoring FLCS <RDY/BSY>. If the automatic
operation to erase protection bits is normally terminated, FLCS will be set to "0x01." While
no automatic verify operation is performed internally to the device, be sure to read the data
to confirm that it has been correctly erased. For returning to the read mode while the
automatic operation after the seventh bus cycle is in progress, it is necessary to use the
hardware reset to reset the flash memory or the device. If this is done, it is necessary to
check the status of protection bits by FLCS <BLPRO 3:0> after retuning to the read mode
and perform either the automatic protection bit erase, automatic chip erase, or automatic
block erase operation, as appropriate.
(Note)
automatic protection bit programming command. The FLCS <RDY/BSY> bit turns
to "0" after entering the seventh bus write cycle.
Software reset is ineffective in the seventh bus write cycle of the
TMP19A61 (rev1.0) 22-521
TMP19A61