tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 379

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(0xFFFF_E808)
(0xFFFF_E809)
(Note) The registers must be byte accessed in setting them.
0: An interrupt is generated when it reaches to the specified fill level.
1: An interrupt is generated when it reaches to the specified fill level or if it is lower than the
0:
1:
HSC0RFC
HSC0TFC
specified fill level at the time new data is written.
An interrupt is generated when it is reaches to the specified fill level or if it exceeds the
specified fill level at the time data is read.
An interrupt is generated when it reaches to the specified fill level.
Function
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Function
Clear RX
FIFO
1: Clear
Always
reads "0."
Clear TX
FIFO
1: Clear
Always
reads "0."
Fig. 14-17 Transmit FIFO Configuration Register
RFCS
TFCS
ｗ
ｗ
7
7
0
0
Fig. 14-16 Receive FIFO Control Register
Select
interrupt
generation
condition
Select
interrupt
generation
condition
TMP19A61(rev. 1.0) 14-378
RFIS
TFIS
6
6
0
0
Always reads "0."
Always reads "0."
5
5
0
0
-
-
R
4
4
0
0
-
-
3
3
0
0
-
-
2
2
0
0
-
-
TMP19A61
FIFO fill level to
generate RX interrupts
00: 4 bytes (2 bytes at
full duplex mode)
01: 1byte
10: 2bytes
11: 3bytes
Note: RIL1 is ignored
when FDPX1:0 = 11 (full
duplex)
FIFO fill level to
generate TX interrupts
00: Empty
01: 1byte
10: 2byte
11: 3byte
Note: TIL1 is ignored
when FDPX1:0 = 11 (full
duplex).
RIL1
TIL1
1
1
0
0
W/R
RIL0
TIL0
0
0
0
0