tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 44

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

6.6
6.7
(Note) "Software interrupt" is different from the idea of "software set" to be used as one of hardware
Single step exceptions and debug breakpoint exceptions are the types of debug exceptions. These
types of exceptions are seldom used in user programs.
Also note that enabling the shadow register set will not be effective in debug exceptions.
Refer to the section "Exception Handling, Debug Exception" of the separate volume "TX19A Core
Architecture" for detailed operation upon generation of debug exceptions.
Two-factor maskable software interrupts (hereinafter referred to simply as "software interrupts") can be
generated by individually setting "1" to the Cause <IP [1:0]> bits of the CP0 register.
Software interrupts can be accepted in no less than three clocks after setting values to the Cause <IP
[1:0]> bits of the CP0 register.
In order for a software interrupt request to be accepted, it is necessary regarding the CP0 register that
its Status <IE> is set to "1" and Status <ERL/EXL> is cleared to "0" while Status <IM [1:0]> is "1." Also,
software interrupts can be individually masked by setting Status <IM [1:0]> of the CP0 register to "0." If
software and hardware interrupts coincide, the hardware interrupt overrides the software interrupt.
Upon software interrupts, when the shadow register set is enabled, SSCR <CSS> will be overwritten by
the value of SSCR <PSS> but the register bank will not be switched because the value of SSCR <CSS>
is not updated. The reason why only the SSCR <PSS> value is updated is because it is necessary to
prevent the register bank from being changed when SSCR <PSS> is overwritten by the value of SSCR
<CSS> due to an ERET instruction executed upon returning from the software interrupt. Software
interrupts are processed in a process flow such as shown in Fig. 6.2.
Debug Exceptions
Maskable Software Interrupts
interrupt factors, as described later. The idea of "Software set" is to generate a hardware
interrupt by setting "01" to IMR00 <EIM00>.
TMP19A61(rev1.0)-6-43
TMP19A61