tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 215

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

ALE (ALESEL = 0)
AD [15 : 0]
(ALESEL = 1)
AD [15 : 0]
When the ALE is 1 clock or 2 clocks
(3) Time for ALE to be asserted
fsys
A[23:16]
AD[15:0]
ALE
/RD
located in the bus control register (BUSCR). The default is 2 clocks. This assert setting
cannot be established for each block in an external area and the same setting is commonly
used in an external address space.
An ALE assertion time is selectable from 1 clock through 4 clocks. The setting bit is
Fig. 8.16 shows the ALE timings with 1 clock or 2 clocks.
Fig. 8.16 Read Operation Timing (t
Lower-order address
Fig. 8.15 Time for ALE to be asserted
tsys
TMP19A61(rev1.0)-8-214
Higher-order address
ｔsys
Data
he ALE timings with 1 clock or 2 clocks
1 clock
2 clocks
Higher-order address
TMP19A61
Data
)