tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 444

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

17.2
WDT counter
WDT interrupt
WDT clear
(software)
WDT counter
WDT interrupt
Internal reset
The watchdog timer consists of the binary counters that are arranged in 22 stages and work
using the f
are 2
watchdog timer interrupt can be generated when an overflow occurs, as shown in Fig. 17.2.1.
Because the watchdog timer interrupt is a non-maskable interrupt factor, NMIFLG <WDT> at the
INTC performs a task of identifying it.
When an overflow occurs, resetting the chip itself is an option to choose. If the chip is reset, a
reset is affected for a 32-state time, as shown in Fig. 17.2.2. If this reset is affected, the clock f
that the clock gear generates by dividing the clock f
an input clock f
Watchdog Timer Interrupt
15
, 2
17
SYS/2
, 2
n
n
19
system clock as an input clock. The outputs produced by these binary counters
SYS/2
and 2
.
32 states (9.48 μs @ f
21
TMP19A61
. By selecting one of these outputs with WDMOD <WDTP1:0>, a
Overflow
Fig. 17.2.1 Normal Mode
Fig. 17.2.2 Reset Mode
Overflow
(rev1.0)
C
= 54 MHz, f
-17-443
Write of clear code
sys
C
of the high-speed oscillator by 8 is used as
= 6.75 MHz, f
sys/2
= 3.375 MHz)
TMP19A61
0
SYS