tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 376

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

LITTLE
BIG
(0xFFFF_E80D)
(0xFFFF_E80E)
HSC0CR
(Note)
Bit symbol
Read/Write
After reset
Function
All the error flags are cleared when read.
The registers must be byte accessed in setting them.
Receive
data bit-8
Fig. 14-13 Serial Control Register (for HSIO0, HSC0CR)
RB8
7
R
0
Parity
0: Odd
1: Even
EVEN
6
0
TMP19A61(rev 1.0)14-375
R/W
1: Enable
Add parity
0: Disable
PE
5
0
Overrun
OERR
R (cleared to "0" when read)
4
0
Parity/
Under run
1: Error
PERR
3
0
Framing
Framing error flag
Parity error/under-run
error flag
Overrun error flag
0
1
0
1
I/O interface input clock selection
HSCLK0 for HSCLK0 input operation
Add/check even parity
FERR
0
1
2
0
Baud rate generator
HSCLK0 pin input
Data transmit/receive at rising
edges of HSCLK0
Data transmit/receive at falling
edges of HSCLK0
Odd parity
Even parity
0: HSCLK0
1: HSCLK0
TMP19A61
SCLKS
1
0
R/W
0:
1: HSCLK0
rate
generator
pin input
Baud
IOC
0
0
Cleared to "0" when
read