tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 100

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

7.4
The port 2 is a general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in
units of bits. Outputs can be set by using the control register P2CR and the function registers P2FC1 and
P2FC2. A reset allows all bits of the output latch P2 to be set to "1," all bits of P2CR, P2FC1 and P2FC2 to be
cleared to "0," and the port 2, to be an input port though it is input/output disabled.
Besides the general-purpose input/output port function, the port 2 performs another function: A0 through A7
function as an address bus and A16 through A23 function as another address bus. To access external memory,
registers P2CR, P2FC1 and P2FC2 must be provisioned to allow the port 2 to function as an address bus.
If the BUSMD pin is set to "L" level during a reset, the port 2 is put in separate bus mode (A16 to A23). If it is set
to "H" level during a reset, the port 2 is put in multiplexed mode (A0 through A7 or A16 through A23).
Port 2 (P20~P27)
P2 read
(Function control)
(Function control)
(Output control)
(Output latch)
(Input control)
P2FC1
P2FC2
P2CR
P2IE
P2
A0~A7
Bus opening
1
0
TMP19A61(rev1.0) 7-99
Fig. 7.3 Port 2(P20~P27)
STOP/RESET
drive disable
A16~A23
1
0
0
1
0
1
TMP19A61
Port 2
P20~P27
(A0~A7/A16~A23)
RESET