tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 569

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

24.10
Output mode/
active-high input
mode
Active-low input
mode
OUTPUT DATA
HSCLK period
HSCLK clock width high (input)
HSCLK clock width Low (input)
TxD data to HSCLK rise or fall*
TxD data hold after HSCLK rise or fall*
RxD data valid to HSCLK rise or fall*
RxD data hold after HSCLK rise or fall*
HSCLK period (programmable)
TxD data to HSCLK rise
TxD data hold after HSCLK rise
RxD data valid to HSCLK rise
RxD data hold after HSCLK rise
INPUT DATA
*HSCLK rise or fall: Measured relative to the programmed active edge of HSCLK.
High-speed Serial Channel Timing
(1) I/O Interface mode (DVCC3=2.7V~3.3V)
HSCLK
HSCLK
RxD
TxD
In the table below, the letter x represents the fsys cycle period, which varies depending on the
programming of the clock gear function.
Parameter
Parameter
HSCLK input mode (HSIO0~HSIO1）
HSCLK output mode (HSIO0~HSIO1)
t
t
OSS
SRD
VALID
0
t
0
SCY
TMP19A61 (rev 1.0)-24-568
Symb
Symb
t
t
t
t
t
t
t
t
t
t
Tsc
SCY
Tsc
OSS
OHS
SRD
HSR
SCY
OSS
OHS
SRD
HSR
ol
ol
H
L
t
SCY
2(x/2)+30
8(x/2)-15
4(x/2)-10
4(x/2)-10
8(x/2)
/2-2x-30
Min
Min
30
45
6x
3x
3x
VALID
Equation
Equation
0
1
1
t
HSR
t
SCH
t
OHS
Max
Max
t
SCL
48.5
-11.5
111
Min
55.5
55.5
Min
59
30
74
27
45
27
0
VALID
54 MHz
54 MHz
2
2
Max
Max
TMP19A61
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VALID
3
3