tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 409
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tmp19a61f10xbg
Manufacturer Part Number
tmp19a61f10xbg
Description
32-bit Tx System Risc Tx19 Family
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP19A61F10XBG.pdf
(575 pages)
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Part Number:
TMP19A61F10XBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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SCL
SDA
<PIN>
INTSBI interrupt
request
Example: When receiving N data words
INTSBI interrupt (after data transmission)
INTSBI interrupt (first to (N-2)th data reception)
INTSBI interrupt ((N-1)th data reception)
INTSBI interrupt (Nth data reception)
INTSBI interrupt (after completing data reception)
Fig. 15.6.3.3 Terminating Data Transmission in the Master Receiver Mode
9
To terminate the data transmission from the transmitter, <ACK> must be set to "0"
immediately before reading the second to last data word. This disables generation of an
acknowledgment clock for the last data word. When the transfer is completed, an interrupt
request is generated. After the interrupt processing, <BC2:0> must be set to "001" and the
data must be read so that a clock is generated for 1-bit transfer. At this time, the master
receiver holds the SDA bus line at the "H" level, which signals the end of transfer to the
transmitter as an acknowledgment signal.
In the interrupt processing for terminating the reception of 1-bit data, the stop condition is
generated to terminate the data transfer.
(Note)
SBI0CR1 ← X X X X 0 X X X
Reg.
End of interrupt
Reg.
End of interrupt
SBI0CR1 ← X X X 0 0 X X X
Reg.
End of interrupt
SBI0CR1 ← 0 0 1 0 0 X X X
Reg.
End of interrupt
Processing to generate the stop condition
End of interrupt
D7
Read out the received data after clearing <ACK> to "0."
1
← SBI0CBR
← SBIDBR
← SBIDBR
← SBIDBR
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
D6
2
TMP19A61
X: Don’t care
D5
3
D4
4
(
rev1.0
Sets the number of bits of data to be received and
specify whether ACK is required.
Reads dummy data.
Reads the first to (N-2)th data words.
Disables generation of acknowledgement clock.
Reads the (N-1)th data word.
Generates a clock for 1-bit transfer.
Reads the Nth data word.
Terminates the data transmission.
D3
)
5
-15-408
D2
6
D1
7
D0
8
TMP19A61
Master to slave
Slave to master
1
Read out the
received data after
setting <BC2:0> to
"001."
Acknowledgment signal
“H” to transmitter
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