tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 258

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

10.4.3 Address Mode
In the dual address mode, the DMAC first performs a read of the source device by storing the data
output by the source device in one of its registers (DHR). It then executes a write on the destination
device by writing the stored data to the device, thereby completing the data transfer.
The unit of data to be transferred by the DMAC is the amount of data (32, 16 or 8 bits) specified in the
TrSiz field of the CCRn. One unit of data is transferred each time a transfer request is acknowledged.
In the dual address mode, the unit of data is read from the source device, put into the DHR and written
to the destination device.
Access to memory takes place when the specified unit of data is transferred. If access to external
memory takes place, 16-bit access takes place twice if the unit of data is set to 32 bits and the bus width
set in the CS wait controller is 16 bits. Likewise, if the unit of data is set to 32 bits and the bus width set
in the CS wait controller is 8 bits, 8-bit access takes place four times.
In the address mode, you can specify whether the DMAC executes data transfers by outputting
addresses to both source and destination devices or it does by outputting addresses to either a source
device or a destination device. The former is called as the dual address mode, and the latter is called as
the single address mode. For TMP19A61, only the dual address mode is available.
Address bus
Data bus
Fig. 10.15 Basic Concept of Data Transfer in the Dual Address Mode
DMAC
DMAC
TMP19A61 (rev1.0)10-257
Address
Data
Destination device
Source device
TMP19A61